Acacia, now part of cisco, provides innovative silicon-based high speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and costOur dsp asics, silicon photonic pics and coherent modules empower cloud and service providers to meet the fast-growing demand for dataWe have assembled a team of cross-functional experts capable of solving the challenges of next generation optical interconnects, resulting in industry-leading, award-winning productsCome join us at cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.
We are looking for an analog/mixed-signal ic design technical lead who will be a key member in a small, dynamic ic design team that develops high speed mixed-signal designs for coherent optical communications productsThis team has track record of developing ultra-high speed (>100 gsps) data converters in latest finfet nodesThis engineer will architect, design, layout, test and productize ultra-deep sub-micron based products.
Essential responsibilities:
Responsible for analog circuit, layout design and testing of analog/mixed signal circuitry for high speed (>25gs/s) and high accuracy analog designs
Work with the mixed-signal and system teams to specify the requirements
Candidate (depending on experience) might be required to lead a large block on a complex chip and mentor some engineers.
Peer review of complex ic designs
Solid design methodology from conception to production
Work with packaging and hardware design team to ensure signal and power integrity specifications are met
Minimum qualifications, experience, skills, education and certifications:
Typically requires an ms degree and more than 10 years of industry experience or a phd and more than 7 years of industry experience.
Design, simulation and measurement of high-speed ics in at least 3 areas below:
High speed time-interleaved adc
Tuned high frequency circuits
Resonant clock circuits, clock distribution and low power clocking techniques
Digital fractional-n phase-locked loop (pll)
High speed time-interleaved dac and output drivers
Digital calibration of analog circuit imperfections
Voltage regulators
Opamps and programmable gain amplifiers
Equalization techniques
Highly desired skills:
Experience with finfet technology.
A) passive component design: inductors, transformers, transmission-lines
B) high-frequency layout experience a plus.
C) floorplanning (power/ground, digital/analog signal routing etc.)
D) custom transistor layout.
E) characterization over pvt (monte-carlo analysis)
F) electromigration analysis (using totem, voltus-fi or equivalent)
G) power and ir drop analysis
Laboratory validation:
A) solid esd laboratory practices and methodology
B) construction of test setup to test specific circuitry
Software experience:
A) cadence (virtuoso)
B) spectre/aps/spectrex
C) layout validation tools (virtuoso or calibre)
D) post-layout extraction (virtuoso or calibre)
E) emx
F) mixed-signal simulations in ams
G) matlab
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But “digital transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)
Day to day, we focus on the give and takeWe give our best, give our egos a break, and give of ourselves (because giving back is built into our dna.) we take accountability, bold steps, and take difference to heartBecause without diversity of thought and a dedication to equality for all, there is no moving forward.
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Posted 10 days ago